# consider a memory unit of size 1024k x 32, where 1st part is the number of memory words where each memory word can store 32 bits of data. find the number of address lines

### Mohammed

Guys, does anyone know the answer?

get consider a memory unit of size 1024k x 32, where 1st part is the number of memory words where each memory word can store 32 bits of data. find the number of address lines from screen.

## CS372: Solutions for Homework 9

## CS372: Solutions for Homework 9

CS372: Solutions for Homework 9 Problem 1

In a 32-bit machine we subdivide the virtual address into 4 segments as follows:

10-bit 8-bit 6-bit 8 bit

We use a 3-level page table, such that the first 10-bit are for the first level and so on.

What is the page size in such a system?

What is the size of a page table for a process that has 256K of memory starting at address 0?

What is the size of a page table for a process that has a code segment of 48K starting at address 0x1000000, a data segment of 600K starting at address 0x80000000 and a stack segment of 64K starting at address 0xf0000000 and growing upward (like in the PA-RISC of HP)?

Solution:

The page field is 8-bit wide, then the page size is 256 bytes.

Using the subdivision above, the first level page table points to 1024 2nd level page tables, each pointing to 256 3rd page tables, each containing 64 pages. The program's address space consists of 1024 pages, thus we need we need 16 third-level page tables. Therefore we need 16 entries in a 2nd level page table, and one entry in the first level page table. Therefore the size is: 1024 entries for the first table, 256 entries for the 2nd level page table, and 16 3rd level page table containing 64 entries each. Assuming 2 bytes per entry, the space required is 1024 * 2 + 256 * 2 (one second-level paget table) + 16 * 64 * 2 (16 third-level page tables) = 4608 bytes.

First, the stack, data and code segments are at addresses that require having 3 page tables entries active in the first level page table. For 64K, you need 256 pages, or 4 third-level page tables. For 600K, you need 2400 pages, or 38 third-level page tables and for 48K you need 192 pages or 3 third-level page tables. Assuming 2 bytes per entry, the space required is 1024 * 2 + 256 * 3 * 2 (3 second-level page tables) + 64 * (38+4+3)* 2 (38 third-level page tables for data segment, 4 for stack and 3 for code segment) = 9344 bytes.

## Problem 2

A computer system has a 36-bit virtual address space with a page size of 8K, and 4 bytes per page table entry.

How many pages are in the virtual address space?

What is the maximum size of addressable physical memory in this system?

If the average process size is 8GB, would you use a one-level, two-level, or three-level page table? Why?

Compute the average size of a page table in question 3 above.

Solution:

A 36 bit address can address 2^36 bytes in a byte addressable machine. Since the size of a page 8K bytes (2^13), the number of addressable pages is 2^36 / >2^13 = 2^23

With 4 byte entries in the page table we can reference 2^32 pages. Since each page is 2^13 B long, the maximum addressable physical memory size is 2^32 * 2^13 = 2^45 B (assuming no protection bits are used).

8 GB = 2^33 B

We need to analyze memory and time requirements of paging schemes in order to make a decision. Average process size is considered in the calculations below.

**1 Level Paging**

Since we have 2^23 pages in each virtual address space, and we use 4 bytes per page table entry, the size of the page table will be 2^23 * 2^2 = 2^25. This is 1/256 of the process' own memory space, so it is quite costly. (32 MB)

**2 Level Paging**

The address would be divided up as 12 | 11 | 13 since we want page table pages to fit into one page and we also want to divide the bits roughly equally.

Since the process' size is 8GB = 2^33 B, I assume what this means is that the total size of all the distinct pages that the process accesses is 2^33 B. Hence, this process accesses 2^33 / 2^13 = 2^20 pages. The bottom level of the page table then holds 2^20 references. We know the size of each bottom level chunk of the page table is 2^11 entries. So we need 2^20 / 2^11 = 2^9 of those bottom level chunks.

The total size of the page table is then:

//size of the outer page table //total size of the inner pages

1 * 2^12 * 4 + 2^9 * 2^11 * 4 = 2^20 * ( 2^-6 + 4) ~4MB

**3 Level Paging**

For 3 level paging we can divide up the address as follows:

8 | 8 | 7 | 13

Again using the same reasoning as above we need 2^20/2^7 = 2^13 level 3 page table chunks. Each level 2 page table chunk references 2^8 level 3 page table chunks. So we need 2^13/2^8 = 2^5 level-2 tables. And, of course, one level-1 table.

The total size of the page table is then:

//size of the outer page table //total size of the level 2 tables //total size of innermost tables

1 * 2^8 * 4 2^5 * 2^8 *4 2^13 * 2^7 * 4 ~4MB

As easily seen, 2-level and 3-level paging require much less space then level 1 paging scheme. And since our address space is not large enough, 3-level paging does not perform any better than 2 level paging. Due to the cost of memory accesses, choosing a 2 level paging scheme for this process is much more logical.

Calculations are done in answer no. 3.

## Problem 3

In a 32-bit machine we subdivide the virtual address into 4 pieces as follows:

8-bit 4-bit 8-bit 12-bit

We use a 3-level page table, such that the first 8 bits are for the first level and so on. Physical addresses are 44 bits and there are 4 protection bits per page. Answer the following questions, showing all the steps you take to reach the answer. A simple number will not receive any credit.

What is the page size in such a system? Explain your answer (a number without justification will not get any credit).

## Topic

Computer organisation and Architecture practice questions how many bits would you need to address 2m memory if the memory is 1m 220, so 2m 221 there are 2m tes

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## How many address bits are required for a 1024 * 8 memory?

Answer: 1024 is similar to 2^10, 10 bits here. And for 8 bits, 2^3 is what sums up. So 3 bits here. So, the total bits is 10+3, 13 bits. Or 1024*8 gives 8192, or 2^13. so 13 bits. If it ain’t a 1024 bits multiplied by 8 bits, or there are 1024 arrays of each size of 8 bit, then 1024 arrays, s...

How many address bits are required for a 1024 * 8 memory?

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Sort Avishek Sharma

B.Tech in Computer Science Engineering, Techno India Agartala (Graduated 2021)Author has 4.1K answers and 5.3M answer views1y

1024 is similar to 2^10, 10 bits here.

And for 8 bits, 2^3 is what sums up. So 3 bits here.

So, the total bits is 10+3, 13 bits.

Or 1024*8 gives 8192, or 2^13. so 13 bits.

If it ain’t a 1024 bits multiplied by 8 bits, or there are 1024 arrays of each size of 8 bit, then 1024 arrays, so 10 bits of addresses will do it.

12.8K viewsView upvotes

Kimaya Kolhe

Author + Blogger & Director at Appeteria Technologies (2013–present)Author has 57 answers and 204.4K answer views4y

Related

How many address lines will a 4k memory have?

Always remember a simple trick for address line calculation for a specific memory capacity;

10 Address lines can access 1K of memory.

if we increase only 1 address line, the memory capacity increases twice than before.

so now 11 address lines can access 2k memory.

Now simple add 1 adress line and twice the memory capacity.

it goes like this->

10 address lines - 1K memory

11 address lines - 2K memory

12 address lines - 4K memory

13 address lines - 8K memory

14 address lines - 16K memory

15 address lines - 32K memory

16 address lines - 64k memory

17 address lines - 128K memory

18 address lines - 256K memory

19

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David Stevens

Computer Engineering Lecturer from 1987 to 1997Author has 3.1K answers and 1.4M answer views1y

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How many address bits are required to represent 8k memory?

I am guessing that you mean “required to address 8k of memory”. My “little trick” to help my memory, is to know that 10 address bits allow the addressing of 1024 bytes (1k) of memory - see the connection? “1024” starts with “10”. So, therefore we need an additional 3 address bits to increase this by a factor of 8 (8 = 2 cubed), giving a total of 13 address bits.

Srinjoy Santra

B. Tech. in Computer Science and Engineering, Kalinga Institute of Industrial Technology (KIIT) (Graduated 2020)Author has 74 answers and 237.4K answer views4y

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What is the memory organisation (1024 bytes) of a computer with four 128*8 RAM chips and 512*8 ROM chips? How many address lines are required to access the memory?

The answer by Alex Ruben is the quickest way. However, I would like to explain a bit more my way. (I hope it makes sense!)

If a memory size is given as m*n,

m = number of words

n = number of bits in a word (i.e. word length)

Memory is usually designed to store or retrieve data in word-length quantities.

Thus, one RAM chip of

128∗8 128∗8

size has 128 words and 8 bits of each word.

128= 2 7 128=27

Thus, 7 address bits are required for 1 RAM chip.

We are given 4 RAM chips. Thus, to select each word separately

2 2 =4 22=4

i.e. 2 more address bits are required.

In total, 7+2=9 7+2=9

address bits are needed for 4 RAM chips.

Similarly, Joe Zbiciak

I have been programming since grade schoolAuthor has 5.1K answers and 35.9M answer views1y

Related

Can a memory chip of 256kb capacity have a 120000h starting address?

It can have any starting address you like. It all comes down to how much hardware you want to build.

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Software engineer and System-on-a-Chip (SoC) architectAuthor has 5.1K answers and 35.9M answer views3y

Related

How many memory locations can 14 address bits access?

You are likely asking the wrong question. Or, perhaps your teacher has phrased their question incompletely, assuming you would fill in context from recent coursework.

Your homework question is likely actually asking how many unique combinations of 14 bits are there.

That's rather different from how much memory you can access with 14 address bits. I could interface an arbitrarily large amount of memory to a machine with only 14 address bits.

Perhaps you think I am being cute about this. That's fine. I'm not.

Consider that the venerable 4116 DRAM has 7 address lines.

The 4116 offers access to 16,384

Balajee Seshadri

24,000,000+ Content views, 35000+ followers, 1700+ AnswersAuthor has 1.5K answers and 24.5M answer views2y

Related

What is the size of memory if there are 32 address lines and 16 data word lines?

As per the calculation it should be 2^32 x 2 bytes (16bit) = 4G x 2 = 8GBytes.

But all the Datasheets and documents mention only 4GBytes

Guys, does anyone know the answer?