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    #11: ATmega328P External Interrupts – Arxterra

    The Real World of External Interrupts

    View Exclusively

    Reading

    The AVR Microcontroller and Embedded Systems using Assembly and C

    by Muhammad Ali Mazidi, Sarmad Naimi, and Sepehr Naimi

    Sections: 10.3, 10.5

    Table of Contents [hide]

    1 External Interrupts

    2 ATmega328P External Interrupt Sense Control

    3 ATmega328P External Interrupt Enable

    4 When Will External Interrupts be Triggered?

    5 PIN Change Interrupts

    6 How a PIN Change Interrupt Works

    7 How to Enable a PIN Change Interrupt

    8 ATmega328P Interrupt Processing (REVIEW)

    9 Programming the Arduino to Handle External Interrupts

    10 Programming the Arduino to Handle Interrupts

    11 Practice Problems

    12 Design Example – Switch Debounce

    12.1 Switch Debounce Solutions

    12.2 Switch Debounce Circuit – a Simple Digital Low Pass Filter

    13 Appendix

    13.1 How I Designed the Debounce Circuit

    13.1.1 Logic Levels

    13.1.2 Rise and Fall Times (Slew Rate)

    External Interrupts

    Review ATmega328P Interrupts Lecture Notes page 4 “Interrupt Basics”

    External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins

    23 Pin Change Interrupts are mapped to the 23 General Purpose I/O Port Pins:

    Port B Group PCINT7 (PB7)  PCINT0 (PB0)

    Port C Group PCINT15 (PC7) PCINT14 (PC6)  PCINT8 (PC0)

    Port D Group PCINT23 (PD7)  PCINT16 (PD0)

    Figure 1: ATmega328P Pinout

    ATmega328P Interrupt Vector Table

    VECTOR NO PROGRAM ADDRESS SOURCE INTERRUPT DEFINITION ARDUINO/C++ ISR() MACRO VECTOR NAME

    1 0x0000 RESET Reset

    2 0x0002 INT0 External Interrupt Request 0 (pin D2) (INT0_vect)3 0x0004 INT1 External Interrupt Request 1 (pin D3) (INT1_vect)4 0x0006 PCINT0 Pin Change Interrupt Request 0 (pins D8 to D13) (PCINT0_vect)5 0x0008 PCINT1 Pin Change Interrupt Request 1 (pins A0 to A5) (PCINT1_vect)6 0x000A PCINT2 Pin Change Interrupt Request 2 (pins D0 to D7) (PCINT2_vect)

    7 0x000C WDT Watchdog Time-out Interrupt (WDT_vect)

    8 0x000E TIMER2 COMPA Timer/Counter2 Compare Match A (TIMER2_COMPA_vect)

    9 0x0010 TIMER2 COMPB Timer/Counter2 Compare Match B (TIMER2_COMPB_vect)

    10 0x0012 TIMER2 OVF Timer/Counter2 Overflow (TIMER2_OVF_vect)

    11 0x0014 TIMER1 CAPT Timer/Counter1 Capture Event (TIMER1_CAPT_vect)

    12 0x0016 TIMER1 COMPA Timer/Counter1 Compare Match A (TIMER1_COMPA_vect)

    13 0x0018 TIMER1 COMPB Timer/Counter1 Compare Match B (TIMER1_COMPB_vect)

    14 0x001A TIMER1 OVF Timer/Counter1 Overflow (TIMER1_OVF_vect)

    15 0x001C TIMER0 COMPA Timer/Counter0 Compare Match A (TIMER0_COMPA_vect)

    16 0x001E TIMER0 COMPB Timer/Counter0 Compare Match B (TIMER0_COMPB_vect)

    17 0x0020 TIMER0 OVF Timer/Counter0 Overflow (TIMER0_OVF_vect)

    18 0x0022 SPI, STC SPI Serial Transfer Complete (SPI_STC_vect)

    19 0x0024 USART, RX USART, Rx Complete (USART_RX_vect)

    20 0x0026 USART, UDRE USART, Data Register Empty (USART_UDRE_vect)

    21 0x0028 USART, TX USART, Tx Complete (USART_TX_vect)

    22 0x002A ADC ADC Conversion Complete (ADC_vect)

    23 0x002C EE READY EEPROM Ready (EE_READY_vect)

    24 0x002E ANALOG COMP Analog Comparator (ANALOG_COMP_vect)

    25 0x0030 TWI 2-wire Serial Interface (I2C) (TWI_vect)

    26 0x0032 SPM READY Store Program Memory Ready (SPM_READY_vect)

    ATmega328P External Interrupt Sense Control

    The INT0 and INT1 interrupts can be triggered by a low logic level, logic change, and a falling or rising edge.

    Figure 2: External Interrupt Control Register A

    This is set up as indicated in the specification for the External Interrupt Control Register A – EICRA as defined in Section 12.2.1 EICRA of the Datasheet. The number “n” can be 0 or 1.

    ISCN1 ISCN0 ARDUINO MODE DESCRIPTION

    0 0 LOW The low level of INTn generates an interrupt request

    0 1 CHANGE Any logical change on INTn generates and interrupt request

    1 0 FALLING The falling edge of INT0 generates an interrupt request

    1 1 RISING The rising edge of INT0 generates an interrupt request

    ATmega328P External Interrupt Enable

    All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register (SREG) in order to enable the interrupt.

    Figure 3: Status Register

    The ATmega 328P supports two external interrupts which are individually enabled by setting bits INT1 and INT0 in the External Interrupt Mask Register (Section 12.2.2 EIMSK).

    Figure 4: External Interrupt Mask Register

    Let’s look at an example. When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

    स्रोत : www.arxterra.com

    AVR Interrupt and External Interrupt : Arduino / ATmega328p

    AVR Interrupt and External Interrupt / Arduino / ATmega328p Microcontroller | Embedded C Register Level Programming Tutorial | AVR Internal Interrupt and External Interrupt Tutorial

    Learn, Implement and Share

    AVR Interrupt and External Interrupt : Arduino / ATmega328p

    Published by Crazy Engineer on May 2, 2021

    Note

    This article is a part of Arduino / ATmega328p Embedded C Firmware Programming Tutorial. Consider exploring the course home page for articles on similar topics.

    Arduino Tutorial Embedded C Register Level Arduino Master Class

    Also visit the Release Page for Register Level Embedded C Hardware Abstraction Library and Code for AVR.

    Introduction

    This section describes the specifics of the interrupt handling as performed in ATmega328P. It also discusses the interrupt vectors available in the chip and how they are used.

    What You Will Learn

    How Iterrupts work in Arduino?

    How CPU Interrupts of AVR ATmega328p chip works?

    What are the different sources of Interrupts in ATmega328p?

    What are the difference between internal and external Interrupts in ATmega328p?

    How Interrupts are enabled or disabled in Arduino/ATmega328p?

    ATmega328P Interrupt Vectors

    The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

    Each Interrupt Vector occupies two instruction words inATmega328/328P. This list determines the priority levels of the different interrupts. The lower the address the higher is the priority level. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.

    Vector No. Program

    Address Source Interrupt Definition

    1 0x0000 RESET External Pin, Power-on,

    Brown-out, Watchdog System Reset

    2 0x0002 INT0 External Interrupt Request 0

    3 0x0004 INT1 External Interrupt Request 1

    4 0x0006 PCINT0 Pin Change Interrupt Request 0

    5 0x0008 PCINT1 Pin Change Interrupt Request 1

    6 0x000A PCINT2 Pin Change Interrupt Request 2

    7 0x000C WDT Watchdog Time-out Interrupt

    8 0x000E TIMER2 COMPA Timer/Counter2 Compare Match A

    9 0x0010 TIMER2 COMPB Timer/Counter2 Compare Match B

    10 0x0012 TIMER2 OVF Timer/Counter2 Overflow

    11 0x0014 TIMER1 CAPT Timer/Counter1 Capture Event

    12 0x0016 TIMER1 COMPA Timer/Counter1 Compare Match A

    13 0x0018 TIMER1 COMPB Timer/Coutner1 Compare Match B

    14 0x001A TIMER1 OVF Timer/Counter1 Overflow

    15 0x001C TIMER0 COMPA Timer/Counter0 Compare Match A

    16 0x001E TIMER0 COMPB Timer/Counter0 Compare Match B

    17 0x0020 TIMER0 OVF Timer/Counter0 Overflow

    18 0x0022 SPI, STC SPI Serial Transfer Complete

    19 0x0024 USART, RX USART Rx Complete

    20 0x0026 USART, UDRE USART, Data Register Empty

    21 0x0028 USART, TX USART, Tx Complete

    22 0x002A ADC ADC Conversion Complete

    23 0x002C EE READY EEPROM Ready

    24 0x002E ANALOG COMP Analog Comparator

    25 0x0030 TWI 2-wire Serial Interface

    26 0x0032 SPM READY Store Program Memory Ready

    When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

    The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during the execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

    A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

    If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program codes can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

    BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

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