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# if the input clock frequency of the 2 bit up counter is 12 khz, then the output clock frequency will be

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### Mohammed

Guys, does anyone know the answer?

get if the input clock frequency of the 2 bit up counter is 12 khz, then the output clock frequency will be from screen.

## Digital Electronics

This is the electronics and communication engineering questions and answers with discussion section on "Digital Electronics" with explanation for various interview, competitive examination and entrance test. Solved examples with detailed answer description, explanation are given and it would be easy to understand - Discussion page for Q.5821.

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## Electronics and Communication Engineering :: Digital Electronics - Discussion

Home » Engineering » Electronics and Communication Engineering » Digital Electronics » Section 2 - Discussion

### Discussion :: Digital Electronics - Section 2 (Q.No.40)

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40.

In a mod-12 counter the input clock frequency is 10 kHz. The output frequency is

[A]. 0.833 kHz [B]. 1.0 kHz [C]. 0.91 kHz [D]. 0.77 kHz Answer: Option A Explanation:

Mod-12 counter is divide by 12 counter. Output frequency = = 0.833 kHz.

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Sri said: (Mar 31, 2018)

Mod 12 has 4 FF then output frequency should be 1.25 KHZ. Please anyone explain the answer.

Piyush Satasiya said: (Aug 10, 2018)

Yes, agree it is 1.25 kHz.

Shiva said: (May 3, 2019)

For a binary counter or M mod counter, the output frequency is f/2^n irrespective of the synchronous and asynchronous counter where f is the input frequency n is a number of flip-flops (only if duty cycle =50%).

Sourav said: (Sep 14, 2019)

It's correct .833khz.

Since mod-12 counter is a shortened modulus counter it does not utilizes all the possible states. Therefore it's a divide by N counter.

Muthu said: (May 29, 2020)

Thanks all for explaining.

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### Current Affairs 2022

स्रोत : www.indiabix.com

## Frequency Division using Divide

Electronics Tutorial about Frequency Division using Divide-by-2 Toggle Flip-flops to produce an Asynchronous Counter ## Frequency Division

Frequency Division uses divide-by-2 toggle flip-flops as binary counters to reduce the frequency of the input clock signal

In the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can be connected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as a binary divider, for Frequency Division or as a “divide-by-2” counter.

Here the inverted output terminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device “feedback” as shown below.

### frequency Division Divide-by-2 Counter It can be seen from the frequency waveforms above, that by “feeding back” the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( ƒ ÷ 2 ) that of the input clock frequency. In other words the circuit produces Frequency Division as it now divides the input frequency by a factor of two (an octave).

This then produces a type of counter called a “ripple counter” and in ripple counters, the clock pulse triggers the first flip-flop whose output triggers the second flip-flop, which in turn triggers the third flip-flop and so on through the chain producing a rippling effect (hence their name) of the timing signal as it passes through the chain.

## The Toggle Flip-Flop

Another type of digital device that can be used for frequency division is the T-type or Toggle flip-flop. With a slight modification to a standard JK flip-flop, we can construct a new type of flip-flop called a Toggle flip-flop.

Toggle flip flops can be made from D-type flip-flops as shown above, or from standard JK flip-flops such as the 74LS73. The result is a device with only two inputs, the “Toggle” input itself and the negative controlling “Clock” input as shown.

### 74LS73 Toggle Flip Flop A “Toggle flip-flop” gets its name from the fact that the flip-flop has the ability to toggle or switch between its two different states, the “toggle state” and the “memory state”. Since there are only two states, a T-type flip-flop is ideal for use in frequency division and binary counter design.

Binary ripple counters can be built using “Toggle” or “T-type flip-flops” by connecting the output of one to the clock input of the next. Toggle flip-flops are ideal for building ripple counters as it toggles from one state to the next, (HIGH to LOW or LOW to HIGH) at every clock cycle so simple frequency divider and ripple counter circuits can easily be constructed using standard T-type flip-flop circuits.

If we connect together in series, two T-type flip-flops the initial input frequency will be “divided-by-two” by the first flip-flop ( ƒ ÷ 2 ) and then “divided-by-two” again by the second flip-flop ( ƒ ÷ 2 ) ÷ 2, giving an output frequency which has effectively been divided four times, then its output frequency becomes one quarter value (25%) of the original clock frequency, (  ƒ ÷ 4 ).

Each time we add another toggle or “T-type” flip-flop to the chain, the output clock frequency is halved or divided-by-2 again and so on, giving an output frequency of 2n where “n” is the number of flip-flops used in the sequence.

Then the Toggle or T-type flip-flop is an edge triggered divide-by-2 device based upon the standard JK-type flip flop and which is triggered on the rising edge of the clock signal. The result is that each bit moves right by one flip-flop. All the flip-flops can be asynchronously reset and can be triggered to switch on either the leading or trailing edge of the input clock signal making it ideal for Frequency Division.

This type of counter circuit used for frequency division is commonly known as an Asynchronous 3-bit Binary Counter as the output on QA to QC, which is 3 bits wide, is a binary count from 0 to 7 for each clock pulse.

In an asynchronous counter, the clock is applied only to the first stage with the output of one flip-flop stage providing the clocking signal for the next flip-flop stage and subsequent stages derive the clock from the previous stage with the clock pulse being halved by each stage.

This arrangement is commonly known as Asynchronous as each clocking event occurs independently as all the bits in the counter do not all change at the same time. As the counter counts sequentially in an upwards direction from 0 to 7. This type of counter is also known as an “up” or “forward” counter (CTU) or a “3-bit Asynchronous Up Counter”. The three-bit asynchronous counter shown is typical and uses flip-flops in the toggle mode. Asynchronous “Down” counters (CTD) are also available.

### Truth Table for a 3-bit Asynchronous Up Counter

Clock Cycle Output Bit Pattern

QC QB QA 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1

Therefore we can see that the output from the D-type flip-flop is at half the frequency of the input, in other words it counts in 2’s. By cascading together more D-type or Toggle Flip-Flops, we can produce a divide-by-2, divide-by-4, divide-by-8, etc. circuit which will divide the input clock frequency by 2, 4 or 8 times, in fact any value to the power-of-2 we want making a binary counter circuit.

स्रोत : www.electronics-tutorials.ws

## [Solved] In the circuit shown, the clock frequency, i.e., the frequen

let Initial states be Q1 = Q2 = 0 $${D_1} = \begin{array}{*{20}{c}} {\overline {{Q_1}} }&{\overline {{Q_2}} } \end{array}$$ D2 = Q1 Hence after 3 clock Home Digital Electronics Sequential Circuits Synchronous Counters Modulus of a Counter

## Question

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz.The frequency of the signal at Q2 is ____ kHz. This question was previously asked in

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## Detailed Solution

let Initial states be Q1 = Q2 = 0 D1=Q1―Q2― D2 = Q1

Hence after 3 clock pulses, the output repeats

It is mod – 3 counter

out frequency =123=4 kHz.

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## More Synchronous Counters Questions

Q1. If the 5-bit ripple counter and 5-bit synchronous counter are having flip-flops with a propagation delay of 20 ns, the maximum delay in the ripple counter (x) and synchronous counter (y) will be:Q2. A __________ counter can be implemented using three flipflops.Q3. A down counter is a counter that counts from ______ to ______ in a downward direction.Q4. Determine fmax for the 4-bit synchronous counter, if tpd for each flipflop is 50ns and tpd for each AND gate is 20ns.Q5. The minimum number of flip-flops needed to construct a BCD decode counter isQ6. In a frequency response, 1 decade means _______ times change in frequency.Q7. A decade counter skips ______.Q8. A decade counter requiresQ9. Assuming that all flip-flops are in reset condition initially, the count sequence observed al QA, in the circuit shown isQ10. For the figure shown, each flip flop has a propagation delay of 10 ns. Determine the total propagation delay from the triggering edge of a clock pulse until a corresponding change can occur in the state of Q3.

## More Sequential Circuits Questions

Q1. Which statement is true for Mealy type Sequence Detector?Q2. Which of the following is true in case of Mealy machine?Q3. If the 5-bit ripple counter and 5-bit synchronous counter are having flip-flops with a propagation delay of 20 ns, the maximum delay in the ripple counter (x) and synchronous counter (y) will be:Q4. In a sequence detector to detect '1010' (Moore type), which of the following is true?Q5. Which of the following is true in case of Moore Machine?Q6. A __________ counter can be implemented using three flipflops.Q7. If the following counter is initially at 0000 state then after 6th clock ABCD will be -Q8. Which of the following condition a D-flip-flop is said to be in a transparent condition?Q9. A down counter is a counter that counts from ______ to ______ in a downward direction.Q10. Which of the following is not capable of storing binary data?

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Mohammed 2 month ago

Guys, does anyone know the answer?