write a verilog code for a 1x4 demultiplexer using if else statement.

Category :

Mohammed

Guys, does anyone know the answer?

get write a verilog code for a 1x4 demultiplexer using if else statement. from screen.

Design of 1 to 4 Demultiplexer using IF

Design of 1 to 4 Demultiplexer using if-else Statements (Behavior Modeling Style) - Output Waveform : 1 to 4 Demultiplexer ...

VHDL Projects

FaceBook Likes

About Me

UNKNOWN

VIEW MY COMPLETE PROFILE

Search Here

Followers

Total Pageviews

Search Here Followers Total Pageviews Archives

▼ 2013 ( 108 ) ► November ( 8 ) ▼ July ( 100 )

The Three Basic Element inside a Computer Chip -

Let's start with making a Semiconductor Chip -

Let's Know about our Semiconductor Industry -

Computer Chips are Every-Where (Application of Ele...

Very Important ACRONYMS & TERMS of Semiconductor I...

Electronics - Trends Setting Points

World of Integrated Chips AND Electronic Design -

Design of 8 to 3 Parity Encoder using if -else sta...

Design of 8 : 3 Parity Encoder using conditional o...

Design of 8 nibble queue using Behavior Modeling S...

Design of 8 nibble Stack using Behavior Modeling S...

Design of Parallel IN - Serial OUT Shift Register ...

FPGA / CPLD Based Project

System Design using Loop Statements (Behavior Mode...

Sample Programs for Basic Systems using Verilog HDL

Design of 4 Bit Adder cum Subtractor using Loops (...

Design of 4 Bit Subtractor using Loops (Behavior M...

Design of 4 Bit Adder using Loops (Behavior Modeli...

Design of Stepper Motor Driver (Half Step) using B...

Design of Stepper Motor Driver (Full Step) using B...

Design of First In - First Out (FIFO) Register usi...

Design of 8 Nibble RAM (memory) using Behavior Mod...

Design of 8 Nibble ROM (Memory) using Behavior Mod...

Sensor Based Traffic Light Controller using FSM Te...

Timer Based Single Way Traffic Light Controller us...

Design of ODD Counter using FSM Technique (Verilog...

स्रोत : verilogbynaresh.blogspot.com

Verilog: 1 to 4 DEMUX (Demultiplexer) Behavioral Modelling using Case Statement with Testbench Code

Verilog Code for 1 to 4 DEMUX Behavioral Modelling using Case Statement with Testbench Code

Latest Post

Verilog: 8 to 3 Encoder Dataflow Modelling with Testbench Code

- January 07, 2023 Post a Comment

Verilog: 1 to 4 DEMUX (Demultiplexer) Behavioral Modelling using Case Statement with Testbench Code

- November 20, 2020

Verilog Code for 1 to 4 DEMUX Behavioral Modelling using Case Statement with Testbench Code

module 1_4_DEMUX( input i, input s1, s0, output [3:0]out ); reg [3:0]out;

always @ (i or s0 or s1)

case ({s1,s0}) 0: out0 = i; 1: out1 = i; 2: out2 = i; 3: out3 = i;

default: out = 4'bxxxx;

endcase endmodule

//Testbench code for 1 to 4 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement

initial begin

// Initialize Inputs

i = 1;s1 = 0;s0 = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

#100; s1=0; s0=1; #100; s1=1; s0=0; #100; s1=1; s0=1; end initial begin #100;

$monitor(“I=%b, s1=%b, s0=%b, out=%b”, I, s1, s0, out);

end endmodule Verilog

Comments

Pages

VLSI - Verilog Programming

Tools Filter Designer

Verilog: Half Adder Behavioral Modelling with Testbench Code

- October 23, 2020

Verilog Code Half Adder Behavioral Modelling module Half_Adder ( input a, b; output sum, carry ); always @(a or b) assign {carry,sum} = a + b; endmodule // test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, sum=%b, carry=%b”, a, b, sum, carry); end endmodule Xilinx Output: Half Adder Verilog Code Behavioral Modelling

VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling

- March 16, 2020

module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule

Verilog: Half Adder Structural/Gate Level Modelling with Testbench

- May 15, 2020

Verilog Code for Half Adder Structural/Gate Level Modelling module half_adder( input i0, input i1, output s, output c ); and(c,i0,i1); xor(s,i0,i1); endmodule //Testbench code for Half Adder Structural/Gate Level Modelling initial begin // Initialize Inputs i0 = 0; i1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; i0 = 0; i1 = 1; #100; i0 = 1; i1 = 0; #100; i0 = 1; i1 = 1; end Output: RTL Schematic: Half Adder Verilog Other Verilog Programs: Go to Index of Verilog Programming

1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench

- May 15, 2020

Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = 0;s1 = 1; #100;d = 1;s0 = 1;s1 = 1; end Output: Verilog 1-4 DEMUX Verilog Code Response Other Verilog Programs: Go to Index of Verilog Programming

Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench

- May 15, 2020

Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming

स्रोत : space-inst.blogspot.com

Verilog Code for Demultiplexer Using Behavioral Modeling

A complete line by line explanation, implementation and the Verilog code for demultiplexer using behavioral architecture and different statements.

Verilog Code for Demultiplexer Using Behavioral Modeling

|| Contents

What is a demultiplexer?

A demultiplexer is a circuit that places the value of a single data input onto multiple data outputs. The demultiplexer circuit can also be implemented using a decoder circuit.

Here we are going to work with 1-to-4 demultiplexer. A 1-to-4 demultiplexer consists of

one input data line,

four outputs, and

two control lines to make selections.

The below diagram shows the circuit of the 1-to-4 demultiplexer. Here a1 and a0 are control or select lines y0, y1, y2, y3 are outputs, and Din is the data line.

Now, let’s observe its truth table –

The values of a1a0 determine which of the outputs are set to the value of Din. When Din=0, all the outputs are set to 0, including the one selected by the valuation of a1a0. When Din=1, the valuation of a1a0 sets the appropriate output (anyone from y0, y1, y2, y3) to 1.

Now that we have thoroughly understood the concepts of the demultiplexer, let’s dive directly into the Verilog code for the demultiplexer.

Different methods used in behavioral modeling of a demultiplexer

There are various styles of writing Verilog code in behavioral modeling for this circuit.

case statements

assignment statements

if-else statements

Here we will be elaborating on the first two. Along the way, we would also emphasize some common design errors.

Verilog code for demultiplexer – Using case statements

The basic building block in Verilog HDL is a module, analogous to the ‘function’ in C. The module declaration is made as follows:

module Demultiplexer_1_to_4_case (output reg [3:0] Y, input [1:0] A, input din);

For starters, module is a keyword. It is followed by an identifier. Identifier=name of the module. After naming the module, in a pair of parentheses, we specify:

the direction of a port as input, output or inout.

Port size, and port name.

Taking into consideration the first line of the code, Demultiplexer_1_to_4_case is the identifier, the input is called port direction. If a port has multiple bits, then it is known as a vector. Hence, [1:0] states that the port named as A is a vector with MSB = 1 and LSB = 0.

The reg data object holds its value from one procedural assignment statement to the next and means it holds its value over simulation data cycles.

Another style of declaration in the port list is to declare the port size and port direction after the module declaration.

module Demultiplexer_1_to_4_case (Y, A, din);

output reg [3:0] Y; input [1:0] A; input din;

[3:0] here signifies that the output is of 4 bits. Next up, since its behavioral modeling style, here comes the always statement.

always @(Y, A) begin

Using the always statement, a procedural statement in Verilog, we will run the program sequentially. (Y, A) is known as the sensitivity list or the trigger list. The sensitivity list includes all input signals used by the always block. It controls when the statements in the always block are to be evaluated. @ is a part of the syntax, used before the sensitivity list. In Verilog, begin embarks and end concludes any block which contains more than one statement in it.

Note that the always statement always @(Y, A) could be written as always @ *. * would mean that the code itself has to decide on the input signals of the sensitivity list.

Then inside always block we write,

case (A)

The case statement in Verilog is analogous to switch-case in C language. First, let us see the general format to write a case statement in Verilog.

case ()case_item1 : case_item2 :

case_item3 : begin

default :

end

endcase

If the expression corresponds to any of the case_item, then those design statements are executed. Otherwise, the default case is executed. So, now we can write

case (A) 2'b00 : begin

Y[0] = din; Y[3:1] = 0;

end 2'b01 : begin

Y[1] = din; Y[0] = 0;

end 2'b10 : begin

Y[2] = din; Y[1:0] = 0;

end 2'b11 : begin

Y[3] = din; Y[2:0] = 0;

end endcase

As we see here in the first case, 2'b00 represents the case when the input A is 2'b00. These cases indicate that, according to the value of A, one of the four statements is selected. The colon then marks the end of a case item and starts the action that must happen in that particular case. The terms begin and end are part of the Verilog syntax if you are writing more than one statement in that block. After this, those statements are mentioned, such as the output port Y[0] should be attached to the din, Y[3:0] to 0, and so on, according to the truth table.

स्रोत : technobyte.org

Do you want to see answer or more ?

Yes No

Mohammed 6 day ago

Guys, does anyone know the answer?

Navigation

Status

Categories

write a verilog code for a 1x4 demultiplexer using if else statement.

Mohammed

Design of 1 to 4 Demultiplexer using IF

FaceBook Likes

About Me

Popular Posts

0 comments :

Post a Comment

Search Here

Followers

Total Pageviews

Verilog: 1 to 4 DEMUX (Demultiplexer) Behavioral Modelling using Case Statement with Testbench Code

Latest Post

Verilog: 8 to 3 Encoder Dataflow Modelling with Testbench Code

Ads

Verilog: 1 to 4 DEMUX (Demultiplexer) Behavioral Modelling using Case Statement with Testbench Code

//Testbench code for 1 to 4 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement

Comments

Pages

Ads

Popular posts from this blog

Verilog: Half Adder Behavioral Modelling with Testbench Code

VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling

Verilog: Half Adder Structural/Gate Level Modelling with Testbench

1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench

Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench

Verilog Code for Demultiplexer Using Behavioral Modeling

Verilog Code for Demultiplexer Using Behavioral Modeling

What is a demultiplexer?

Different methods used in behavioral modeling of a demultiplexer

Verilog code for demultiplexer – Using case statements

Last Posts

Random Posts