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    write a verilog code for a 1x4 demultiplexer using if else statement.

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    Design of 1 to 4 Demultiplexer using IF

    Design of 1 to 4 Demultiplexer using if-else Statements (Behavior Modeling Style) - Output Waveform :   1 to 4 Demultiplexer ...

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    Design of 1 to 4 Demultiplexer using IF-ELSE statements (Behavior Modeling Style). (Verilog CODE).

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    Design of 1 to 4 Demultiplexer using if-else Statements (Behavior Modeling Style) -

    Output Waveform :   1 to 4 Demultiplexer

    Verilog CODE -

    //-----------------------------------------------------------------------------

    //

    // Title       : demultiplexer1_4

    // Design      : verilog upload 2

    // Author      : Naresh Singh Dobal

    // Company     : nsdobal@gmail.com

    // Verilog Programs & Exercise by Naresh Singh Dobal.

    //

    //-----------------------------------------------------------------------------

    //

    // File        : 1 to 4 Demultiplexer using if else statement.v

    module demultiplexer1_4 ( din ,sel ,dout );

    output [3:0] dout ; reg [3:0] dout ; input din ; wire din ; input [1:0] sel ; wire [1:0] sel ;

    always @ (din or sel) begin

    if (sel==0)

    dout = {din,3'b000};

    else if (sel==1)

    dout = {1'b0,din,2'b00};

    else if (sel==2)

    dout = {2'b00,din,1'b0};

    else

    dout = {3'b000,din};

    end endmodule Newer Post Older Post Home

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    स्रोत : verilogbynaresh.blogspot.com

    Verilog: 1 to 4 DEMUX (Demultiplexer) Behavioral Modelling using Case Statement with Testbench Code

    Verilog Code for 1 to 4 DEMUX Behavioral Modelling using Case Statement with Testbench Code

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    Verilog: 1 to 4 DEMUX (Demultiplexer) Behavioral Modelling using Case Statement with Testbench Code

    - November 20, 2020

    Verilog Code for 1 to 4 DEMUX Behavioral Modelling using Case Statement with Testbench Code

    module 1_4_DEMUX( input i, input s1, s0, output [3:0]out ); reg [3:0]out;

    always @ (i or s0 or s1)

    case ({s1,s0}) 0: out0 = i; 1: out1 = i; 2: out2 = i; 3: out3 = i;

    default: out = 4'bxxxx;

    endcase endmodule

    //Testbench code for 1 to 4 DEMUX (DeMultiplexer) Behavioral Modelling using Case Statement

    initial begin

    // Initialize Inputs

    i = 1;s1 = 0;s0 = 0;

    // Wait 100 ns for global reset to finish

    #100;

    // Add stimulus here

    #100; s1=0; s0=1; #100; s1=1; s0=0; #100; s1=1; s0=1; end initial begin #100;

    $monitor(“I=%b, s1=%b, s0=%b, out=%b”, I, s1, s0, out);

    end endmodule Verilog

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    Verilog Code for Demultiplexer Using Behavioral Modeling

    A complete line by line explanation, implementation and the Verilog code for demultiplexer using behavioral architecture and different statements.

    Verilog Code for Demultiplexer Using Behavioral Modeling

    || Contents

    What is a demultiplexer?

    A demultiplexer is a circuit that places the value of a single data input onto multiple data outputs. The demultiplexer circuit can also be implemented using a decoder circuit.

    Here we are going to work with 1-to-4 demultiplexer. A 1-to-4 demultiplexer consists of

    one input data line,

    four outputs, and

    two control lines to make selections.

    The below diagram shows the circuit of the 1-to-4 demultiplexer. Here a1 and a0 are control or select lines y0, y1, y2, y3 are outputs, and Din is the data line.

    Now, let’s observe its truth table –

    The values of a1a0 determine which of the outputs are set to the value of Din. When Din=0, all the outputs are set to 0, including the one selected by the valuation of a1a0. When Din=1, the valuation of a1a0 sets the appropriate output (anyone from y0, y1, y2, y3) to 1.

    Now that we have thoroughly understood the concepts of the demultiplexer, let’s dive directly into the Verilog code for the demultiplexer.

    Different methods used in behavioral modeling of a demultiplexer

    There are various styles of writing Verilog code in behavioral modeling for this circuit.

    case statements

    assignment statements

    if-else statements

    Here we will be elaborating on the first two. Along the way, we would also emphasize some common design errors.

    Verilog code for demultiplexer – Using case statements

    The basic building block in Verilog HDL is a module, analogous to the ‘function’ in C. The module declaration is made as follows:

    module Demultiplexer_1_to_4_case (output reg [3:0] Y, input [1:0] A, input din);

    For starters, module is a keyword. It is followed by an identifier. Identifier=name of the module. After naming the module, in a pair of parentheses, we specify:

    the direction of a port as input, output or inout.

    Port size, and port name.

    Taking into consideration the first line of the code, Demultiplexer_1_to_4_case is the identifier, the input is called port direction. If a port has multiple bits, then it is known as a vector. Hence, [1:0] states that the port named as  A is a vector with MSB = 1 and LSB = 0.

    The reg data object holds its value from one procedural assignment statement to the next and means it holds its value over simulation data cycles.

    Another style of declaration in the port list is to declare the port size and port direction after the module declaration.

    module Demultiplexer_1_to_4_case (Y, A, din);

    output reg [3:0] Y; input [1:0] A; input din;

    [3:0] here signifies that the output is of 4 bits. Next up, since its behavioral modeling style, here comes the always statement.

    always @(Y, A) begin

    Using the always statement, a procedural statement in Verilog, we will run the program sequentially. (Y, A) is known as the sensitivity list or the trigger list. The sensitivity list includes all input signals used by the always block. It controls when the statements in the always block are to be evaluated. @ is a part of the syntax, used before the sensitivity list. In Verilog, begin embarks and  end concludes any block which contains more than one statement in it.

    Note that the always statement always @(Y, A) could be written as always @ *. * would mean that the code itself has to decide on the input signals of the sensitivity list.

    Then inside always block we write,

    case (A)

    The case statement in Verilog is analogous to switch-case in C language. First, let us see the general format to write a case statement in Verilog.

    case ()case_item1 : case_item2 :

    case_item3 : begin

    default :

    end

    endcase

    If the expression corresponds to any of the case_item, then those design statements are executed. Otherwise, the default case is executed. So, now we can write

    case (A) 2'b00 : begin

    Y[0] = din; Y[3:1] = 0;

    end 2'b01 : begin

    Y[1] = din; Y[0] = 0;

    end 2'b10 : begin

    Y[2] = din; Y[1:0] = 0;

    end 2'b11 : begin

    Y[3] = din; Y[2:0] = 0;

    end endcase

    As we see here in the first case, 2'b00 represents the case when the input A is 2'b00. These cases indicate that, according to the value of A, one of the four statements is selected. The colon then marks the end of a case item and starts the action that must happen in that particular case. The terms begin and end are part of the Verilog syntax if you are writing more than one statement in that block. After this, those statements are mentioned, such as the output port Y[0] should be attached to the din, Y[3:0] to 0, and so on, according to the truth table.

    स्रोत : technobyte.org

    Do you want to see answer or more ?
    Mohammed 6 day ago
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    Guys, does anyone know the answer?

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